integrated circuit systems, inc. general description features AV9107C-13 block diagram cpu frequency generator a v 91 0 7 -13 revb05219 7 the AV9107C-13 offers a tiny footprint solution for generating two simultaneous clocks. the av 9107c-13 uses a 20 mhz crystal to generate two pll synthesis outputs of 20 and 40 mhz. the output enable pin will tristate the 40 mhz output when low (maintaining the 20 mhz output runing in both logic levels). the power pin takes the device to a low current condition, shutting off the pll and forcing both outputs low, when the pd# pin is low. there is a built-in pull-up on both the oe and pd# inputs. the device has advanced features which include on-chip loop filters, tristate outputs, and power-down capability. a minimum of external components - two decoupling capacitors and an optional ferrite bead - are all that are required for jitter- free operation. ? patented on-chip phase-locked loop with vco for clock generation ? provides two synthesized clocks ? generates 20 and 40 mhz output frequencies. ? on-chip loop filter ? low power cmos technology ? single +3.3 or +5 volt power supply ? 8-pin soic package pin configuration note: crystal is 20 mhz
2 AV9107C-13 pin descriptions functionality (at 14.318) mhz reference frequency input) frequency accuracy and calculation the accuracy of the frequencies produced by the av9107c depends on the input frequency and the desired actual output frequency. the formula for calculating the exact output frequency is as follows: for example, to calculate the actual output frequency for a video monitor expecting a 44.900 mhz clock and using a 14.318 mhz input clock, the closest a/b ratio is 69/22, which gives an output of 44.906 mhz (within 0.02% of the target frequency). generally, the a v9107 can produce frequencies within 0.1% of the desired output. pin number pin name type description 1 oe input output enable - tristates the 40 mhz output when low. pull-up 2 gnd pwr ground. 3 x1/clk0 input crystal input or input clock frequency. typically 20mhz crystal. 4 x2 output crystal output (no connect when clock used.). 5 pd# input power down. shuts off chip when low outputs are driven low. internall pull-up. 6 clk1 output clock 1 output 40mhz with 20mhz crystal. 7 vdd pwr digital power supply (+5v dc). 8 clk2 output clock2 output, divided by 2 from clock1 output, for 20mhz with 20mhz crystal. output is synthesized. oe clk1 clk2 0 20 mhz tristate 1 20 mhz 40 mhz output frequency = input frequency x a b allowable input and output frequencies the input frequency should be between 12 and 40 mhz and the a/b ratio should not exceed 24. the output should fall in the range of 12 to 80 mhz for clk1 dnd clk2. (see specification for 3.3v and 5v condition details). output enable the output enable feature tristates the clk1 output clock pin. this places the selected output pins in a high inpedance state to allow for system level diagnostic testing. the divide- by-2 output of clk2 remains active on the AV9107C-13 for any oe state. power down the power down pin shuts off the entire chip to save current. a few milliseconds are required to reach full functioning speed from a power down state. where a = 2, 3, 4 ... 128, and b = 2, 3, 4 ...32.
3 AV9107C-13 note 1: parameter is guaranteed by design and characterization. not 100% tested in production. note2: av 9107c-13 with the power down pin low (active). note3: absolute jitter measured as the shortest and longest period difference to the mean period of the sample set. electrical characteristics at 5.0v operating v dd = +4.5v to +5.5v; t a =0c to 70c unless otherwise stated absolute maximum ratings avdd, vdd referenced to gnd . . . . . . . . . . . . . . . 7v operating temperature under bias. . . . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c voltage on i/o pins referenced to gnd. . . . . . . . . . . gnd -0.5v to vdd +0.5v power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 watts stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.8v input high voltage v ih 2.0 - - v input low current i il v in =0v - 6.0 16.0 a input high current i ih v in =v dd 2.0 - 2.0 a output low voltage v ol i ol =10ma - 0.25 0.40 v output high voltage, note 1 v oh i oh =-30ma 2.4 3.25 - v output low current, note 1 i ol v ol =0.8v 22.0 35.0 - ma output high current, note 1 i oh v oh =2.0v - -50.0 -35.0 ma supply current i dd no load - 18.0 40.0 ma output frequency change over supply and temperature f d with respect to typical frequency note 1 - 0.002 0.05 % stand by supply current i ddstdby note 2 - 12.0 50.0 a pull-up resistor, note 1 r pu v in = v dd -1v - 380.0 800.0 k ohms ac characteristics output rise time 0.8 to 2.0v, note 1 t r 15pf load - 0.65 1.60 ns output fall time 2.0 to 0.8v, note 1 t f 15pf load - 0.55 1.2 ns rise time 20% to 80% vdd, note 1 t r 15pf load - 1.5 3.5 ns fall time 80% to 20% vdd, note 1 t f 15pf load - 1.1 2.2 ns duty cycle, note 1 d t 15pf load 45.0 - 55.0 % jitter, one sigma, note 1 t jis 10,000 samples - 40.0 120.0 ps jitter, absolute, notes 1, 3 t jab 10,000 samples -500.0 200 500.0 ps input frequency, note 1 f i 14 20 40 mhz output frequency, note 1 f o clock1 28 40 80 mhz power-up time, note 1 t pu -130300s
4 AV9107C-13 electrical characteristics at 3.3v operating v dd = +3.0v to +3.7v; t a =0c to 70c unless otherwise stated dc characteristics parameter symbol test conditions min typ max units input low voltage v il --0.20v dd v input high voltage v ih 0.7vdd - - v input low current, note1 i il v in =0v - 2.5 7.0 a input high current, note 1 i ih v in =v dd -2.0 - 2.0 a output low voltage, note 1 v ol i ol =6ma - 0.15 0.1xv dd v output high voltage, note 1 v oh i oh =-5ma 0.85xv dd 0.92xv dd -v output low current, note 1 i ol v ol =0.2v dd 15.0 22.0 - ma output high current, note 1 i oh v ol =0.7v dd - -17.0 -10.0 ma supply current, note 1 i dd unloaded - 11.0 25.0 ma standby supply current, notes 1, 2 i ddstdby - 13.0 40.0 a output frequency change over supply and temperature, note1 f d with respect to typical frequency - 0.002 0.01 % pull-up resistor, note 1 r pu v in = v dd - 0.5v - 0.55 1.0 m ohms ac characteristics rise time 20% to 80% vdd, note 1 t r 15pf load - 2.0 3.4 ns fall time 80% to 20% vdd, note 1 t f 15pf load - 1.2 2.2 ns duty cycle, note 1 d t 15pf load @ 50% 42 - 52 % jitter, one sigma, note 1 t jis 10,000 samples - 40.0 120.0 ps jitter, absolute, notes 1, 3 t jab 10,000 samples 500.0 200 500.0 ps input frequency, note 1 f i 12 20 25 mhz output frequency, note 1 f o clock1 24 40 50 mhz power-up time, note 1 t pu - 265 500 s note 1: parameter is guaranteed by design and characterization. not 100% tested in production. note2: av 9107c-13 with the power down pin low (active). note3: absolute jitter measured as the shortest and longest period difference to the mean period of the sample set.
5 AV9107C-13 ordering information AV9107C-13cs08 example: 8-pin plastic soic package xxx xxxx-ppp m x#w lead count & package width lead count=1, 2 or 3 digits w=.3? soic or .6? dip; none=standard w idth package type s=soic pattern number (2 or 3 digit number for parts with rom code patterns, if applicable) device t ype (consists of 3 or 4 digit numbers) prefix ics, av=s tandard device; gsp=genlock device
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